1. Field of the Invention.
The present invention relates to decoding circuits employed with memory arrays and more particularly to decoding circuits for use in integrated circuits comprising memory arrays with a surplus of rows of memory cells which may be substituted for rows of memory cells which do not operate properly.
2. Description of the Prior Art.
A manufacturer of integrated circuits may often reduce overall manufacturing costs of its product by reducing the rejection rate for defective individual parts. One way to reduce the rejection rate is through ever finer refinement of manufacturing processes. Such refinement, though, is subject to the laws of diminishing returns. For example, a given integrated circuit may contain several thousand individual electronic components, such as transistors, diodes and the like. It may prove relatively easy and inexpensive to reduce the probability of a particular integrated circuit having one or more defective components to a certain percentage but increasingly difficult or expensive to improve the rejection rate beyond that point. Still, the presence of only one or two defective components out of thousands of components on an integrated circuit will dictate the rejection of that integrated circuit and potentially thousands of other integrated circuits.
Another solution to reducing the rejection rate, without expensive refinements of manufacturing processes, is to provide auxiliary, sometimes called redundant, circuit components on the integrated circuit. This solution is practical where testing can locate, within certain bounds, the defective component, and the circuit is readily reconfigurable to allow substitution of an auxiliary component for the defective component. Integrated circuit matrix memory arrays, including static random access memories, are such circuits.
Memory arrays are characterized by the regular repetition of components. A very substantial portion of an integrated memory array is taken up by substantially identical memory cells disposed in regular rows and columns.
Decoding circuits are provided on the integrated circuit memory for operating on various combinations of electrical signals provided as inputs to the integrated circuit to generate signals within the integrated circuit for causing activation of a specific group of cells in the array. The decoder circuit includes a plurality of row decoders, each of which is adapted to provide a row select signal in response to a particular known set of electrical signals.
The foregoing combinations of electrical signals typically comprise sets of logic signals. A logic signal is an electrical signal which represents two states, termed 0 and 1. Each logic signal represents a selected one of these states by being set at a certain predetermined voltage level, for example Vo for 1. Another voltage level may then be taken as 0. Typically, the voltage level for logical 1 is higher (i.e., more positive) than the voltage level for logical 0. Each logic signal represents one bit of information.
While combinations of logic signals may be provided to integrated circuits in various ways, one common way, seen in digital computers, is to provide a separate conductive path for each logic signal. Different combinations, by virtue of activating different rows of memory cells through the decoder, represent what are called memory addresses. A particular row of cells actuated is the memory address location. Each memory address is defined by the same number of logic signals.
A computer will address a memory address location in a time segment known as a memory cycle. Accordingly, one set of conductive paths, known as address lines, provides for transmission of all memory addresses. The set of address lines is referred to as the address bus. One memory address appears on the address bus in each memory cycle.
The repetitive nature and "addressable" characteristics of integrated circuit array memories are the aspects of these integrated circuits which are exploited to substitute auxiliary components. Because one row of memory cells is substantially like another row of memory cells, it does not matter which row stores any particular information. What matters is that it does store it and that the information can be located thereafter.
Substitution of auxiliary components for regular components requires reconfiguration of the circuit so that a memory address causes activation of a previously unused row of memory cells and ceases to cause activation of the defective row.
In certain static random access memories, row decoders incorporate integrated NPN-type bipolar multi-emitter transistors. Memory row select signals are generated on the collectors thereof in response to the transistor being in its off state. Control of the ON/OFF state of each multi-emitter transistor is effected through control of the voltage potential appearing on each emitter thereof. If a voltage difference between any emitter and the base of the transistor exceed the threshold voltage for the transistor, the transistor turns on. Only if the threshold potential is not exceeded between any base to emitter junction is the transistor off. Accordingly, providing high signals to all of the emitters of a multi-emitter transistor in a row decoder is required to turn the transistor off.
The potential level on each emitter of the multi-emitter transistor is transmitted thereto on actuation lines. One actuation line is provided for each state of each address signal. Thus, there are two actuation lines for each address line, a primary actuation line which is high when the signal on the address line represents logic 1 and low otherwise, and a complementary actuation line which is high when the signal on the address line represents logic 0 and low otherwise. One emitter from each of the multi-emitter transistors for one-half of the row decoders is electrically connected to the primary actuation line corresponding to a given address line. One emitter from each of the multi-emitter transistors in all of the remaining row decoders is electrically connected to the complementary actuation line corresponding to the same address line. Accordingly, half the multi-emitter transistors will have a high potential appearing on one emitter for any memory address. This pattern is repeated for each address line. One-half of the multi-emitter transistors have an emitter connected to the primary actuation line for an address line, the other half have one emitter connected to the complementary actuation line for the address line. However, connection of the actuation lines is done so that no two row drivers are connected to the same combination of actuation lines. Only one row decoder will receive all high signals on all the emitters of its multi-emitter transistor for any one memory address. That row decoder generates a row select signal in response to its multi-emitter transistor turning off.
The electrically conductive paths supplying power to each row decoder, and the electrically conductive paths corresponding to the actuation lines, can be caused to lie on the surface of the integrated circuit and thus be accessible for reconfiguration. In prior art devices, both conductive paths are configured to achieve circuit reconfiguration.
Reconfiguration is achieved by incorporating an element, such as a fusible link, in a surface conductive path on the integrated circuit. Such fusible links, or configuration links, may be opened by a variety of steps, e.g., exposure to laser light to vaporize the link. Opening a link breaks the electrical connection between, for example, one element and the balance of the circuit. Opening a configuration link is used to remove a portion of a circuit element, or a substantial collection of elements, from the overall circuit.
In certain prior art devices, configuration links are used to connect each row decoder to a power source. Opening the configuration link for a particular row decoder prevents that row decoder from developing a select signal. Auxiliary row decoders for each auxiliary row of memory cells are provided. Each auxiliary row decoder has a multi-emitter bipolar NPN transistor and is substantially similar to regular row decoders. However, the number of emitters in the auxiliary multi-emitter transistor equals the total number of actuation lines. Each emitter is connected to one actuation line by a configuration link. As long as all the configuration links are closed, one-half of the emitters will be low for each address and no select signal is generated. The auxiliary decoder generates an auxiliary memory row select signal only after one half of the configuration links connected to its emitters are opened, leaving a pattern of closed configuration links corresponding to a memory address.
In order to provide for substitution of auxiliary rows of memory cells into the matrix memory, the number of configuration links provided equals 2.sup.n +2nK (where n equals the number of address lines and K equals the number of auxiliary rows of memory cells). While configuration links can be made quite small, they do occupy valuable space on the surface of the integrated circuit. Further, configuration links for row decoders and those disposed on actuation lines are located in different parts of the integrated circuit, introducing complications in reconfiguration of the circuit. An additional problem with such prior art devices is excessive variation in voltage levels on terminals where select signals are to be generated. Select signal voltages vary as a function of the number of auxiliary decoders programmed. Because actuation signals are generated by current sources, programming reduces the number of emitters from which current is drawn thus producing more sharply defined select signals. In devices with a large number of auxiliary decoders, it sometimes proves necessary to program a certain minimum number of auxiliary decoders whether needed or not.